What are known as single-transistor cells are used in dynamic random access memories. To further increase the storage density for future technology generations, the feature size is reduced from generation to generation. This leads to a reduced surface area of the storage capacitor of the memory cell, with the result that the capacitance of the capacitor is reduced accordingly. For this reason, it is necessary for the capacitance of the capacitor to remain at least constant despite the reduced feature size.
To solve this problem, it has been proposed to etch deeper trench-like structures (deep trenches). However, limits are disadvantageously imposed on the extent to which the capacitance of the capacitor can be increased in this way, since an anisotropic etching process cannot provide structures of any desired depth and with any desired aspect ratio.
Furthermore, it has been proposed to introduce what are known as grain elements or hemispherical silicon grains HSG in a lower region of the trench-like recess in order to increase the first electrode surface area. However, an increase in the surface area by the introduction of grain elements is disadvantageously associated with a considerable outlay on technology, which leads to an increase in costs during the fabrication of memory cells.
Furthermore, it has also been proposed to widen the trench-like recess in a lower region of the trench, for example by means of a side wall etch, in order to increase the surface area of a storage capacitor which forms a memory cell. However, the amount of additional capacitor surface area which can be achieved by a side wall etch (bottle etch) is limited.